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PLC810PG hiperplc ? family www.powerint.com august 2009 continuous mode pfc & llc controller with integrated half-bridge drivers product highlights features ? highly integrated, eliminates external components ? frequency and phase synchronized pfc and llc ? reduced noise and emi ? ripple current reduction in pfc output capacitor ? edge collision-avoidance simplifes layout ? comprehensive pfc and llc fault handling and current limiting ? proprietary continuous conduction mode pfc for high effciency with low component cost ? high effciency zero voltage switching (zvs) llc ? off-time pfc control eliminates ac input sensing components ? confgurable, precise dead time control and frequency limit ? prevents hard mosfet switching ? tight llc duty cycle symmetry for balanced o/p diode currents ? lead and halogen free green package applications ? 32 to 60 lcd tv power supplies ? off-line 150 w to 600 w effciency-optimized power supplies ? led street lighting description the PLC810PG is a combined pfc and llc off-line controller with integrated high voltage half-bridge drivers. figure 1 shows a simplifed schematic of a PLC810PG based power supply where the llc resonant inductor is integrated into the figure 1. typical application circuit C lcd tv power supply. transformer. the pfc section of the PLC810PG is a universal input continuous current mode (ccm) design that does not require a sinusoidal input reference, thereby reducing system cost and external components. the dc-dc controller drives an llc resonant topology. this variable frequency controller provides high effciency by switching the power mosfets at zero voltage, eliminating most switching losses. the llc controller is built around a current controlled oscillator with a control range selected to support the traditional frequency of operation found in televisions. to ensure zero voltage switching, the dead time of the llc switching in the PLC810PG is tightly toleranced and can be adjusted with an external resistor. the highside/lowside duty cycle is also closely matched to provide balanced output currents reducing output diode cost. a typical PLC810PG llc design operates at 100 khz (under nominal conditions). depending on the llc circuit design, the switching frequency can vary from half to three times the nominal operating frequency as a result of line and load changes. the pfc converter is frequency locked to the llc to minimize noise and electromagnetic interference. increasing the pfc frequency in synchronization with the llc at light loads reduces the current at which the pfc boost converter llc feedback circuit PLC810PG gateh gatel hb ac in dc out vcc vccl vcchb gatep isl isp fbp vcomp gndp link gnd fmax vref fbl gndl pi-5044a-121708 pfc gate driver + standby supply
rev. f 08/09 2 PLC810PG www.powerint.com becomes discontinuous improving light load operation and reducing power line harmonics. pfc and llc primary side fault management is provided. the phase of the pfc pwm output is dynamically adjusted relative to the llc phase such that the switching edges do not coincide with noise sensitive events in the pwm and llc timing circuits. this edge-collision avoidance technology simplifes power supply layout and improves performance. phase synchronization reduces emi spectral components and reduces ripple current in the pfc capacitor.
rev. f 08/09 3 PLC810PG www.powerint.com pin description vcc pins vcc vcc powers the small signal analog circuitry inside the ic. a bypass capacitor must be connected from the vcc pin to the gnd pin. this capacitor needs to be a 10 m f ceramic capacitor, or a parallel combination of a 10 m f electrolytic capacitor and a 0.1 m f ceramic capacitor. vccl vccl is the supply pin for the llc low side driver. it powers only the llc low side mosfet driver and the communications circuitry between the analog circuitry and the llc drivers. a 1 m f ceramic bypass capacitor must be connected from the vccl pin to the gndl pin. this capacitor provides the instantaneous current for turning on the gate of the llc low-side mosfet. vcchb vcchb is the foating supply pin for the llc high-side driver, which is referenced to the hb pin. the hb pin is in turn connected to the llc mosfet half-bridge center point. a 1 m f ceramic bypass capacitor must be connected from the vcchb pin to the hb pin. this capacitor provides the instantaneous current for turning on the gate of the high side llc mosfet. in a typical application, vcc is connected to the standby supply. vccl should be connected to the vcc pin through a 5 w resistor for noise immunity. vcchb is connected to the standby supply through a series combination of a high voltage diode and a 5 w resistor. this diode plus resistor combination charges the 1 m f decoupling capacitor whenever the llc low- side mosfet is on. the resistor limits the peak instantaneous charging current. see r42 and d8 in figure 4. gnd pins gnd gnd is the return node for all analog small signals. all small signal pin bypass capacitors must be connected to this pin via short traces. this pin must have a single point connection, via a dedicated trace to the pfc current sense resistor, which in turn must be placed close to the pfc mosfet. it must not be connected to any other point in the pfc/llc power train. the vcc bypass capacitor must also be connected to this pin. gndp gndp is the return for the pfc gate drive signal only . this pin must be connected on the pcb directly to the gnd pin. gndl gndl is the return for the llc low side gate driver only. this pin must be connected to the llc low side mosfet source pin, with a dedicated trace, and a small ferrite bead. this pin must be connected to the gnd pin via a 1 w resistor for noise immunity. the vccl bypass capacitor must also be returned to this pin. other pins hb half-bridge pin. this pin is the return of the llc high side mosfet driver. it must be connected to the center of the half- bridge formed by the llc mosfets. the vcchb bypass capacitor must also be returned to this pin. isp current sense, pfc. it is for sensing the negative voltage on the current sense resistor (which describes pfc inductor current). this sense resistor is connected between pfc mosfet source and bridge - terminal. the signal must pass through an rc low-pass flter with a time constant between 100 and 200 ns. the resistor must be no greater than 150 w due to internal offset current requirements for the isp pin. the average inductor current (measured over several switching cycles) is used for the pfc control algorithm. this pin also implements pulse-by-pulse current limiting. isl current sense, llc. this pin is for sensing transformer primary current, to detect llc overload. it should be connected to the current sense resistor, which is connected between the llc low side mosfet source pin and the bottom side of the trans- former primary. the signal must pass through an rc low-pass flter with a time constant between 200 ns and 1 m s. the capacitor in the low-pass flter must be connected to the gnd pin. the current limit has 2 levels, a lower, slow current limit for output overload, and a higher, fast current limit for component failure protection. the series resistor in the low-pass flter should be 1 k w or greater to limit current into the isl pin. gatep gate drive output signal for the pfc mosfet gate drive circuit. gatel gate drive for the low side llc mosfet. gateh gate drive for the high side llc mosfet. vref 3.3 v reference pin for the llc feedback circuitry. a 1 m f ceramic decoupling capacitor must be connected from the v ref pin to the gnd pin. fbp the feedback pfc pin is connected to the external resistor divider that senses pfc output voltage. this is a non-inverting input to a transconductance amplifer. the transconductance amplifer output is connected to the vcomp pin, to which the feedback compensation is also connected. a 10 nf decoupling capacitor must be connected from the fbp pin to the gnd pin. vcomp this pin is the connection point for pfc feedback loop components. the voltage on this pin is used as an input to the pfc controller multiplier. the linear voltage range for this pin is nominally 0.5 v to 2.5 v, where higher voltage signifes less power. fbl llc feedback pin. current entering this pin determines llc switching frequency. it has a thevenin equivalent circuit of nominally 0.65 v and 3.3 k w . fbl must be decoupled to the gnd pin with a 1 nf capacitor. note that this capacitor forms a pole with the input resistance.
rev. f 08/09 4 PLC810PG www.powerint.com fmax this pin is for programming maximum llc frequency with a resistor to vref. if the frequency commanded by the fbl pin current exceeds 95% of the programmed maximum frequency, the llc high and low side drivers turn both llc mosfets off. this pin must be decoupled to the gnd pin with a 1 nf capacitor. rsvd1, rsvd2, and rsvd3 rsvd1 must be connected to vref. rsvd2 and rsvd3 must be connected to the gnd pin. pi-5040-012709 fmax gnd isp vref rsvd1 ga tep vcc gndp gndl ga tel nc ga teh fbp nc vcomp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 17 isl fbl gnd rsvd3 rsvd2 vccl nc hb vcchb figure 2. pin numbering and designation (top view).
rev. f 08/09 5 PLC810PG www.powerint.com figure 3. block diagram of PLC810PG. reserved pins are not shown. block diagram figure 3 shows a block diagram of the functional elements that make up the PLC810PG. the reserved pins are not shown in the diagram. those pins are reserved for pi use during manufacture and testing. the PLC810PG pfc control blocks and circuits are shown on the upper half of the block diagram, while the llc control blocks are shown on the lower half. some of the functional blocks are shared. PLC810PG power block the PLC810PG is powered through vcc and vccl pins. the vccl pin powers the llc driver while vcc powers the rest of the device. vcc pin must be supplied by a voltage between v uvlo(+) and 15 v. the provided supply is continuously compared against the v uvlo(+) and v uvlo(-) thresholds to start/stop the PLC810PG. when vcc is above the v uvlo(+) threshold the PLC810PG de- asserts the undervoltage lockout (uvlo) signal allowing the device to start. if vcc falls below v uvlo(-) , the uvlo signal is asserted, shutting down the PLC810PG. the vccl pin powers the llc driver, and vcchb provides the charge for the llc high-side mosfet for gate drive. an internal linear regulator is used to generate a 3.3 v rail to power the low voltage circuits inside the PLC810PG. the 3.3 v is brought outside on the vref pin allowing external low voltage circuits to be powered by the PLC810PG. pi-5041-112608 + - + - + - + - + - + - + - (6) gatep (7) vcc (4) vref (13) vcchb (12) gateh (14) hb (16) vccl (9) gndl v oc v ovh ota v in(h) /v in(l) v sd(h) v sd(l) llc off ovl fault llc off llc fault v isl(f) v isl(s) soft start clamp ovl fault ov fault v fbpref pfc inhibit oc fault llc clock v ref pfc fault v uvlo(+) v uvlo(-) isp (3) vcomp (1) fbp (23) gnd (2,19) isl (22) (8) gndp (10) gatel dvga and lpf pwm reset internal reference generator inversion 3.3 v linear regulator one shot 4096 cycles + - clamp 1.2 v fbl (20) fmax (21) llc current feedback ramp and clock generator dead time generator non- overlap generator phase alignment uvlo
rev. f 08/09 6 PLC810PG www.powerint.com PLC810PG pfc control block the PLC810PG pfc is a boost converter which conditions the average input current to make it (typically) sinusoidal and in phase with the input voltage. in normal operation the pfc operates in continuous conduction mode (ccm). under light load, depending on the pfc inductor value, the converter may enter a discontinuous conduction mode (dcm). the PLC810PG pfc controller does not need to sense the input voltage. the PLC810PG pfc controller exploits the fact that the input voltage (v in ) is effectively constant over a few adjacent switching cycles, because the input is changing at 60 hz while the switching frequency is 1500 times higher. using the average input voltage and output voltage values, the off-time for the boost converter is: d d v v 1 of f o in = - = ] g the input current is the same as the inductor current (sensed current), thus from the previous equation, it can be deduced that: i v d i v in in of f sens e o # = in order to make the input impedance look resistive, the input current must be proportional to the input voltage: i v r n i e n = thus, d off has to be controlled by: d v r i of f o e sens e # = c m if (d off ) changes slowly with the input voltage, the average current will be in-phase with the input voltage. the PLC810PG pfc block controls the pfc off-time (d off = (1Cd)). the output voltage needs to be regulated and r e needs to be adjusted as a function of the load and the input voltage. the PLC810PG pfc has two inputs: ? the feed-back pfc output voltage is reduced by a resistor divider and sensed and via the fbp pin. ? the instantaneous inductor current, sensed via the isp pin. the pfc output voltage is sensed at the fbp pin through an external resistive divider so that the desired dc boost voltage (typically 385 v) is reduced to match the internally generated v fbpref (2.2 v) reference voltage. the fbp input pin and the v fbpref voltage are inputs to an operational transconductance amplifer (ota). the output of the ota drives the vcomp pin, allowing external compensation of the low frequency voltage loop. the purpose of the phase alignment block is to set the edges of the pfc mosfet gate drive signal to avoid the llc converter switching edges. this eliminates switching-noise coupling between llc and pfc circuits. the compensation components are connected between vcomp and the analog ground pin (gnd). the vcomp pin is used to apply compensation to the low frequency voltage loop. the voltage developed across the pfc current sense resistor and applied to the isp pin is compared against an overcurrent threshold (which has built in hysteresis). this implements a pulse-by-pulse current limit to protect the pfc mosfet against overcurrent. the isp pin voltage is also averaged (over several switching cycles), and used as an input to the pfc multiplier. the discrete variable gain amplifer, dvga/lpf block is responsible for averaging the isp pin voltage (over several switching cycles) and implementing a multiplier as part of the pfc control loop, under control of the vcomp signal. using the feedback voltage on fbp, pfc and llc circuit protection is provided: ? pfc overvoltage protection : the feedback voltage on the fbp pin is compared against an overvoltage threshold (v ov(h) ). if the voltage at the fbp pin is greater than v ov(h) , the pfc mosfet gate signal is turned off immediately, and held off for at least one cycle. when fbp drops below v ov(h) , pfc switching recommences. ? minimum boost voltage detection : the feedback voltage on fbp is compared against a minimum boost voltage thresh - old (v in(h) /v in(l) ). the pfc is inhibited if the fbp voltage is below v in(l) . the gate of the pfc mosfet is driven via gatep if the fbp voltage is above v in(h) ). this is done to prevent pfc startup in brownout or during ac failure conditions. ? minimum boost voltage for llc startup : the feedback voltage on fbp is compared against an llc shutdown voltage threshold (v sd(h) )/ v sd(l) ). this inhibits llc startup until the pfc output voltage is close to regulation. the purpose of v sd(l) is to shutdown the llc when the pfc output voltage is low (~64% of nominal), which may occur during ac dropout, shutdown, or overload conditions. ? pfc open-loop protection : the fbp pin includes a high- impedance (5 m f ) pull-down resistor to protect against a foating fbp pin resulting in an open-loop condition. plc810 llc control block the PLC810PG llc controller supports half-bridge topologies. the llc circuit relies on two switches in a half-bridge topology driving a resonant tank (llc) and power transformer. the llc circuit has two resonant frequencies: the series resonant frequency and the parallel resonant frequency. typically, an llc converter is designed to operate at a switching frequency which is slightly higher than the series resonant frequency when at nominal input voltage. in this operating region, the mosfet switching can be performed at zero voltage, reducing the switching losses. in the normal mode of operation, the llc controller will vary its switching frequency around a narrow range of frequencies to regulate the output voltage. feedback and maximum frequency limit the PLC810PG llc controller has nominal operating frequency of 100 khz. for voltage regulation, with input voltage and load variations, the operating frequency will vary and may exceed 250 khz. the maximum frequency set by the resistor on fmax pin is typically chosen to be two to three times the nominal operating frequency. the appropriate maximum frequency is set
rev. f 08/09 7 PLC810PG www.powerint.com using a resistor connected between the vref pin and the fmax pin using the curve in figure 15. the resistor on the fmax pin also sets the llc dead time interval (see figure 14). the fbl pin provides output voltage regulation. as such the current entering this pin modulates the switching frequency. more current forces a higher switching frequency. the fmax pin sets an upper limit for the switching frequency to ensure zero voltage switching. minimum switching frequency is determined by the adjusting minimum bias applied to the fbl pin. if the external feedback circuit attempts to push the llc controller to a frequency equal to or higher than the maximum frequency limit set by the resistor at fmax pin, the llc mosfet gate driver outputs are turned off until the current into the fbl pin drops below the fmax pin current. the gate outputs are turned off synchronously with the clock for whole cycles. llc soft start the llc controller implements a soft start to prevent excessive currents during startup, and to prevent overshoot on the output when the feedback loop comes into operation. the soft start time is determined by external components on the fbl pin. in the event of an llc fault turning off the llc circuit, the external circuit is allowed to discharge, initiating a new soft start. when the soft start signal is asserted, the fbl pin is pulled up to v ref (3.3 v), keeping the current applied to the fbl pin to maximum. during the soft start cycle, the llc outputs turn on and the switching frequency slowly decays from its maximum to the nominal operating point. llc overcurrent detection (isl pin) overcurrent in the llc converter is detected via a sense resistor in series with the low side of the transformers primary winding. when the overcurrent condition is detected, the llc mosfets are turned off. the overcurrent detection has two thresholds; fast overcurrent threshold (v isl(f) ) and slow over- current threshold (v isl(s) ). the fast overcurrent threshold is triggered by abnormally high current. the llc is shutdown immediately if the pulse on the isl pin exceeds this threshold. the slow overcurrent threshold is lower than the fast over- current threshold. the slow overcurrent response is triggered and the llc is shutdown if the isl pin voltage exceeds this threshold for eight consecutive clock cycles. typically the (v isl(f) ) threshold is used to detect catastrophic failures such as shorted components, while the slow v isl(s) threshold is used to detect overload conditions. this over- current detection circuit prevents the llc converter from operating in the capacitive region of the llc, thus avoiding failure of the converter components from overheating. other llc control blocks the non-overlap (dead time) generator creates two non- overlapping signals with equal on-times to drive the llc mosfets. the drive signal for the two llc mosfets is symmetrical with a 50% duty cycle. the dead time block is used both by the pfc and llc to control the dead time of the switching function. the dead time in the PLC810PG is confgurable via the fmax pin. the dead time allows zero voltage switching, reducing the body diode losses in the switching mosfets and minimizing the reverse recovery time of the body diodes. start-up once the vcc voltages reach the startup voltage (v uvlo(+) ), the PLC810PG starts switching the pfc mosfet and the pfc output ramps to its nominal value. when the pfc boost voltage (sensed through fbp pin) raises the fbp pin voltage above the llc start threshold (v sd(h) ), the llc circuit is enabled and the llc soft start begins.
rev. f 08/09 8 PLC810PG www.powerint.com figure 4. PLC810PG lcd tv power supply application circuit, pfc circuit control inputs and llc stage. gateh hb gatel isl vccl vref rsvd1 fmax fbl vcc gndl gndp u6 PLC810PG vcchb gatep isp fbp vcomp nc nc nc rsvd2 rsvd3 gnd gnd 13 12 14 10 u7b ltv817a 22 16 5 4 21 20 7 9 6 3 23 v cc gatep isp controller gnd 1 11 15 24 17 18 2 19 8 b+ b- t2 24 v j3-1,2,3 5 v_stby 12 v j3-9,10 rtn j3-4,5,6,7,8 tp27 pi-5275-061109 u7a ltv817a q13 mmbt3906 q12 si4408dy d11 ll4148 q15 mmbt3904 q14 mmbt3906 ovp 5 v main j4-1 r59 0.1 ? 2 w r56 10 ? r38 4.7 ? r37 4.7 ? r42 10 ? r44 10 ? r48 2.2 k? 1/8 w r55 1 ? r39 768 k? 1% r40 768 k? 1% r41 768 k? 1% r43 768 k? 1% r46 768 k? 1% d8 uf4005 r58 10 ? r47 1 k? r49 51.1 k? 1% r51 22.1 k? 1% r53 19.1 k? 1% l6 ferrite bead (3.5 4.45 mm) q10 irfib5n50 lpbf gatel r62 3.9 k? r63 1 k? r72 1 k? r69 10 k? r60 100 ? r61 10 k? r71 100 ? r70 10 k? r73 10 k? r57 10 ? r67 470 k? r68 10 k? 1% r66 82.5 k? 1% r74 10 k? r64 162 k? 1% u8 lm431aim r65 1 k? c50 220 nf c48 1 f 50 v c52 100 f 35 v l8 3.3 h c43 10 f 25 v c46 2.2 nf 200 v c47 22 nf 200 v c49 10 nf 200 v c44 10 f 25 v c53 1800 f 35 v c39 22 nf 1250 v bead 3 ferrite bead d16 ll4148 r54 1.8 k? c36 1 nf 200 v r52 19.1 k? 1% c27 1 f c23 1 f 25 v c28 22 nf 200 v q16 2n3906 c26 10 f 50 v c25 10 nf 200 v c24 1 nf 200 v c31 1 f 25 v c32 100 nf 50 v c29 10 f 50 v c33 1 f 25 v c30 1 nf 200 v l7 ferrite bead (3.5 4.45 mm) c34 1 nf 200 v c35 1 nf 200 v c40 100 nf 630 v c45 22 nf 200 v c38 1800 f 35 v c37 1800 f 35 v 13 7,8 9,10 11,12 14 6 5 d9a 16ctt100 d10a d9b vr6 2mm5256b-7 30 v d12 ll4148 d13 ll4148 vr7 2mm5245b-7 15 v d10b 16ctt100 r45 150 ? q11 irfib5n50 lpbf d17 ll4148 d18 ll4148 r50 22.1 k? 1% tp24 tp20 tp21 tp23 tp18 tp26
rev. f 08/09 9 PLC810PG www.powerint.com figure 5. PLC810PG lcd tv power supply application circuit, input circuit and pfc power stage. figure 6. PLC810PG lcd tv power supply application circuit, standby supply. pi-5186-012909 rl1 bridge + brownout bridge - b+ b- bridge - isp bridge + n e l v cc gatep controller gnd v cc b- r1 680 k? r2 680 k? r3 680 k? r4 0 ? r9 4.7 k? r7 2.2 ? r6 0.11 ? 2 w r8 0.11 ? 2 w l2 10 mh l4 480 h l3 29 uh br1 gbj806-f 600 v d14-15 1n4007 l1 10 mh c1 330 pf 250 vac c4 470 nf 275 vac c10 1 f 25 v c9 220 f 450 v c11 20 nf 500 v c7 1 f 630 v c6 330 pf 250 vac c2 330 pf 250 vac c5 330 pf 250 vac c3 470 pf 275 vac d2 stth8s06d d1 1n5406 d4 dl4007 d3 1n4007 q3 fmmt591 q1 fmmt491 q2 spp21n 50c3in bead 1 ferrite bead bead 2 ferrite bead f1 5 a rv1 320 vac rt1 5 ? t o tp2 tp4 tp1 tp3 d s bp en r13 470 ? r18 10.2 k? 1% sw1 remote on/off r23 10 k? 1% r34 3.9 k? r17 1 k? r36 1 k? u1a ltv817a u3b pc817x4j u3a pc817x4j u2b ltv817a u1b ltv817a r22 470 ? r12 22 k? r30 680 k? c21 1 nf 200 v c22 100 nf 50 v q7 mmbt3904 q6 mmbt3904 vr3 zmm5232b-7 5.6 v q9 mmbt3904 r29 680 k? r28 620 k? r35 10 k? r24 226 k? 1% r25 3.9 m? r21 100 k? r20 220 k? r32 10 k? r26 100 k? r16 22 k? r14 22 k? r15 330 k? r10 220 k? 1/2 w r19 1.3 m? r11 4.7 m? 1/2 w r31 2.2 k? c13 20 nf 500 v c12 1 nf 1 kv c17 1 f 25 v c51 100 pf 200 v c16 470 f 35 v c42 1 nf 250 vac tinyswitch-iii u4 tny275pn c20 100 nf 50 v c18 100 nf 50 v c19 10 f 50 v c14 2200 f 10 v c15 220 f 25 v rtn j4-2,3 5 v standby j4-4 standby ovp b- gatel brownout b+ tp28 v cc l5 3.3 h d6 sb540 vr2 zmm5245b-7 15 v vr1 p6ke 150a vr4 zmm5204b-7 10 v t1 1 9, 10 nc 6, 7 2 3 4 5 ee25 pi-5187-061109 q5 mmbt 3906 q8 mmbt3904 remote on/off 5 v ovp 5 v regulation remote on/off 5 v regulation q4 bst52ta u5 lm431aim 2% d7 uf4003 d5 uf4007 5 v ovp u2a ltv817a r27 33 ? r33 1 k? vr5 zmm5231b-7 5.1 v tp5 tp6 tp7
rev. f 08/09 10 PLC810PG www.powerint.com applications example circuit description figures 4, 5, and 6 show the schematic of a typical 280 w lcd tv power supply application using hiperplc and tinyswitch-iii. the psu contains pfc + llc stage using a PLC810PG which provides the high power outputs, plus a standby power supply using a tny275pn. the design has 4 outputs: 12 v and 24 v, 5 v main and 5 v standby. the 5 v main and 5 v standby are provided by the tinyswitch-iii fyback circuit. see the typical application section of the tinyswitch-iii data sheet found on the power integrations website for a description of a tinyswitch-iii fyback converter. the psu has a standby input signal, which enables the main converter (PLC810PG). emi filtering and rectifcation capacitors c42, c1, c5, c3, c4, c2, c6 and common mode chokes l1 and l2 perform emi fltering. diode bridge br1 rectifes the input ac with d14 and d15 providing a separate full-wave rectifed signal for the brownout circuit. inrush limiting thermistor rt1 provides inrush limiting. it is bypassed by a relay (rl1) which is driven by the power supply remote-on signal. the use of a relay increases effciency by approximately 1%. diode d3 provides an inrush path to the bulk capacitor c9 that bypasses the pfc inductor l4 to prevent it from saturating. pfc stage the main pfc inductor l4, mosfet q2, boost diode d2, and bulk cap c9, form a pfc boost converter. capacitor c8 and r5 damp reverse recovery ringing on d2. inductor l4 uses a small low cost sendust core. two key advantages of this continuous mode pfc design are that the low ripple current allows the use of: 1. high b sat material (such as low-cost sendust), allowing fewer turns which saves copper cost and reduces size. 2. low-cost magnet wire rather than litz wire. diode d2 is a low-cost silicon ultrafast pfc boost diode. components q1, q3, c10 and r7 form the gate drive circuit. see description under recommended pfc gate drive circuit. pfc current sense resistors r6 and r8 are clamped by d3 and d4 to protect the current sense input of the controller ic during inrush. capacitor c11 is positioned close to the pfc mosfet and diode to limit the size of the high frequency loop around components q2, d2 and c9. this reduces emi. low-loss flm capacitor c7 functions as the input capacitance to the pfc boost converter, and also flters emi. llc stage llc input stage mosfets q10 and q11 form the llc half-bridge. they are driven directly by the plc810 via gate resistors r56 and r58. capacitor c39 is the primary resonating capacitor, and should be a low-loss type rated to tolerate the highest rms current seen at maximum load. transformer t2 has a large built-in leakage inductance which acts with c39 to form the series resonant tank. capacitor c40 is used for local bypassing, and is located directly adjacent to q10 and q11. resistor r59 provides primary current sensing to the controller for overload protection. llc outputs the secondary ouputs of transformer t2 are rectifed and fltered by d9, d10, c38, c39 and c53 to provide the +12 and +24 v outputs. switched +5 v main output mosfet q12 is used to switch the output of the +5 v logic supply. the ac signal from one side of the 12 v output rectifer is used to drive q12 via r60, r61, d11, and c43. capacitor c44 provides fltering near the output connection. bias regulator / remote on/off and brownout shutdown circuit components q4, u1, c17, and associated components constitute the bias regulator and provide the remote on-off function. darlington transistor q4, r14, and vr2 form a simple emitter follower voltage regulator that is switched via optocoupler u1. capacitor c17 limits the rate of rise of the bias voltage. transistor q5 and r20 quickly discharge c17 when optocoupler u1 is turned off. on the secondary, optocoupler u1 is turned on via q8 when the standby signal is high. this turns on the pfc llc stages. a brownout shutdown circuit is provided to actively shutdown the psu when the output turns off due to a brownout condition. this circuit operates by sensing the ac input voltage together with the presence of the gatel signal from the llc controller. during a brownout condition, the pfc output voltage will drop until the vfb pin voltage drops to inh, turning off the llc stage. if at this point the ac voltage is below 82 vac, the brownout circuit will turn off the plc810 via the bias regulator, preventing the pfc from charging up the bulk capacitor again, restarting the llc, and repeating the cycle (and creating output voltage glitches). resistor r24, r26, r28-30, c21, vr4, and q7 are used to sense the ac input voltage. the voltage threshold of this circuit is set below the turn-on threshold of the standby/primary bias converter. suffcient ac voltage turns on q7, discharging capacitor c22, which is charged via r15. components r32, r35, and q9 sense the switching gatel signal. transistor q9 discharges capacitor c22 when the switching signal is present.
rev. f 08/09 11 PLC810PG www.powerint.com when the ac input voltage is low, q7 and q9 turn off, allowing c22 to charge. transistor q6, r21, and vr3 sense the voltage on c22. when c22 has charged suffciently, q6 turns on, turning off the primary bias supply via q5, shutting down the plc810 and thus the pfc and llc stages. controller figure 4 shows the circuitry around the u13 main controller ic, which provides control functions for the input pfc and output llc stages. pfc control the pfc boost stage output voltage is fed back to the fbp pin of the PLC810PG via resistors r39-41, r43, r46, and r50. a 10 nf capacitor (c25) flters noise. capacitor c26, c28 and r48 provide frequency compensation for the pfc. the pfc current sense signal from resistors r6 and r8 is fltered by r45 and c24. the pfc drive signal is routed to the main switching mosfet via resistor r44, which damps any ringing in the pfc drive signal caused by the trace length from the PLC810PG to the pfc gate drive circuitry. bypassing/ground isolation see gnd pins and vcc pins under the section pin description. capacitors c29 and c32 provide decoupling for the vcc pin. capacitor c31 provides decoupling for the vccl pin. resistor r37 is an optional resistor that provides additional fltering for the vcc pin. this will help reject any noise picked up by long vcc traces from the standby supply. capacitors c24, c25, c32, c29, c30, c31, c33, c34, c35 must be connected to the correct ground pins, and be connected with short traces to the PLC810PG. see section pin description. resistor r55 separates the gnd and gndl pins. together with ferrite bead l7, it provides high frequency isolation between gnd and gndl pins. the gatel output gate drive for the low- side llc mosfet q11 returns to gndl through ferrite bead l7. the gateh output gate drive for the high-side llc mosfet q10 returns to hb through ferrite bead l6. this bead is optional, but provides symmetry with l7. llc control feedback from the llc output sense/error amplifers circuits is provided by optocoupler u7. resistor r54 is the optocoupler load. diode d16 allows the optocoupler to pull up on the llc feedback pin (fbl) only. see llc controller section for the description of the functions performed by of r54, c36, r53, r51, r49, and c27. the llc current sense signal from resistor r59 is fltered by r47 and c35. capacitor c23, r42, and d8 provide the booststrap supply for the llc high side mosfet driver. see gnd pins and vcc pins under the section pin description. llc secondary control circuits figure 4 shows the secondary control schematic for the llc stage. voltage feedback the llc converter 12 v and 24 v outputs are sensed, weighted, and summed by resistors r64, r66, and r68. resistor r62 is the main gain-setting resistor. resistor r63 and c45 form a phase-lead compensator which extends the feedback loops crossover frequency and increases the phase margin. resistor r67, c46 and c47, in conjunction with r68 set the low- frequency compensation. capacitor c48 is a soft fnish capacitor that reduces output overshoot at start up, by conducting during the output rise time. it does not affect the main feedback loop characteristics. ovp zener diodes vr6-7 and d12, d13 sense any overvoltage condition in the 12 v or 24 v outputs. an overvoltage signal from either output is used to trigger a bipolar latch (q14, q15, r70, r73), which turns on transistor q13. this transistor is used to deactivate the remote on-circuit which turns off the primary bias, and hence the PLC810PG. power supply block functions and key design details pfc control section the pfc controller uses continuous conduction mode, with an off-duty-cycle control algorithm. this approach removes the requirement for input ac voltage sensing. the off-time is proportional to the product of the average inductor current (averaged over several switching cycles), and the error amp output. this automatically shapes the average input current, to the same shape as the input ac voltage. the PLC810PG pfc circuit is frequency and phase locked to the llc circuit. PLC810PG employs collision avoidance technology, where the pfc edges straddle those of the llc so that simultaneous edge transitions in both the pfc and llc sections are prevented. this reduces interference between pfc and the llc circuits. the pfc section has 2 input pins: a current sense input (isp pin), and a voltage feedback input (fbp pin). there are 2 output pins. a vcomp pin for placing the feedback compensation components, and a mosfet gate signal output designed to work with an external mosfet driver. inductor current is sensed via the isp pin which monitors the negative voltage developed across the pfc current sense resistor. this resistor is connected to the pfc mosfet source pin. the current is averaged over several switching cycles and is used for the pfc control algorithm. this pin also implements a cycle-by-cycle current limit to protect the pfc mosfet in the event of a short-circuit. the rc flter with 100-200 ns time constant attenuates high frequency switching noise, but must be fast enough to detect a saturating pfc inductor in order to protect the pfc mosfet. pfc output voltage is sensed by the fbp pin via a resistor voltage divider network. the fbp pin is connected to the input
rev. f 08/09 12 PLC810PG www.powerint.com of an operational transconductance amplifer (ota). the output of this ota is connected to the vcomp pin. the feedback loop operates to keep the voltage on the fbp pin (and therefore the pfc output voltage) to a fxed value, depending on the resistor divider ratio. when the pfc output voltage is higher than the set point, the transconductance amplifer will source current, raising the voltage on the vcomp pin. when the pfc output voltage is lower than the set point, the transconductance amplifer will sink current, lowering the voltage on vcomp pin. the gain of the stage is equal to the product of the ota gain (g m ), and the impedance of the network connected to the vcomp pin. the pfc controller senses the voltage on the vcomp pin. a higher voltage tends to reduce the pfc mosfets duty cycle, while a lower voltage tends to increase it. the vcomp pin has a linear operating range of 0.5 v to 2.5 v, and is scaled and multiplied by the average inductor current to set d off , the off-duty-cycle of the pfc gate signal. during closed-loop steady state operation, the vcomp voltage is a function of the line voltage and the pfc load. a low voltage on vcomp signifes high power, while a high voltage corresponds to low power. the vcomp pin is internally connected to an input of a multiplier which is part of the pfc modulator. the linear range of this pin is 0.5 v to 2.5 v. 0.5 v signifes maximum power, and 2.5 v signifes minimum power. the fbp pin has 3 start-up and shutdown voltage thresholds. 1. inh C inhibits pfc start-up at low ac input voltage. 2. v sd(h) C inhibits llc start-up after pfc start-up. llc start-up is delayed until the pfc output voltage is close to its regulation set point. 3. v sd(l) C shuts down the llc converter when the bulk cap has discharged to a low voltage C typically at the end of holdup time. before pfc start-up, the voltage on the bulk cap is approx- imately equal to the peak of the input voltage, and inh acts as an ac undervoltage lockout. after the pfc starts, the pfc output voltage no longer tracks the input voltage and there is no low ac voltage shutdown function. for a typical design with a pfc voltage set point of 385 v, the pfc is inhibited when bulk voltage <100 v (typical), which is equivalent to vac <71 v (typical). llc start-up is inhibited until the pfc output voltage reaches 368 v (typical). for the same design, the llc will shut down when the pfc output voltage drops below 246 v (typical). llc controller section the llc converter is a variable frequency converter (an llc converters output power decreases as frequency increases). the designer needs to set the minimum and maximum frequencies of the PLC810PG to suit the power train. fmax pin the fmax pin is connected via a programming resistor to the vref pin. this resistor programs the current into the fmax pin. this pin has a nominal thevenin equivalent circuit of 0.65 v and 1.5 k w . the programmed current into the fmax pin controls two parameters: 1. the llc drive (gatel and gateh) dead-time. the smaller the resistor value, the greater the current and the higher the maximum frequency, see figure 15. 2. the maximum llc operating frequency. when the fbl pin current increases above the fmax pin current, the llc mosfets will be shut down. switching will restart when the fbl pin current drops below the fmax pin current. the dead-time should be longer than the actual voltage rise and fall times of the llc half-bridge center-point (longest times at minimum load). if the programmed dead-time is shorter than the actual rise and fall times, the mosfets will no longer operate in the zvs region, and losses will increase. dead-times somewhat longer than this required minimum have very little impact on effciency. during long dead-times the body diodes of the llc switching mosfets will conduct current just before turn-on; the additional conduction loss is very small compared to other losses. the fmax pin programming resistor sets both dead- time and maximum frequency. setting a longer dead-time than that required at no-load is the recommended approach if a lower maximum frequency is desired . if the required dead-time is very long, and the resulting f max is lower than that required for light load regulation (for the worst case at maximum input voltage), then the solution is to limit f max and allow the llc to enter burst-mode under light load (maximum frequency) in order to keep the output in regulation. maximum input voltage occurs during a 100-0% load step which causes the pfc output voltage to overshoot to vov(h) triggering the pfc output overvoltage protection circuit (which is nominally 105% of the pfc nominal voltage set point). for a typical design, an llc converter requires an f max of 1.5x ~ 2x the nominal operating frequency (measured at full load and nominal input voltage). if burst-mode regulation is required for light load operation, the fbl pin resistors must be chosen such that the maximum current driven by the feedback loop into the fbl pin is greater than the fmax pin current (set by the fmax pin resistor). when the fbl pin current is greater than the fmax pin current, the llc gate drivers turn off both mosfets. during line/load conditions that require higher frequency than f max to maintain regulation, the llc converter will go into hysteretic burst-mode to maintain regulation. when burst mode is used, care must be taken to ensure that during startup, the peak primary currents do not trigger primary over current (isl pin). this is because switching frequency cannot be higher than f max (even during soft start) and the peak primary currents with a low soft start frequency will therefore be higher.
rev. f 08/09 13 PLC810PG www.powerint.com figure 7. typical llc feedback network. fbl pin the fbl pin is the voltage regulation feedback pin. it sinks current in normal operation. the greater the input current, the higher the llc switching frequency. the characteristic of frequency versus the size of shunt resistor (connected to vref) is given in figure 16. the fbl pin has a thevenin equivalent circuit of nominally 0.65 v and 3.3 k w . it should be noted that the 1 nf decoupling capacitor, c fbl (see figure 7), in conjunction with the 3.5 k w input resistance presented by the fbl pin, form a pole in the llc transfer function. this needs to be considered as part of the llc feedback loop. to insure loop stability the 1 nf capacitor should not be increased. a typical feedback network uses a tl431 and an optocoupler for output regulation. the optocoupler regulates current provided to the fbl pin. a resistor network between the optocoupler and the fbl pin sets the minimum, maximum, and start-up currents into the fbl pin. in figure 7 optocoupler u1b is connected to the fbl pin through a resistor network comprised of resistors r1, r2, r3, r4, and the capacitor c start . c start is active only during soft start and can be ignored during normal operation. copto is a flter capacitor that reduces noise from the long optocoupler traces. the value (r3 + r4) sets the minimum fbl pin current and therefore minimum llc frequency, f min (when the optocoupler is turned off). this occurs at the end of holdup time, when the bulk capacitor has discharged down to 64% (nominal) of the regulation set point. the maximum fbl pin current (and therefore the maximum llc frequency that the feedback loop can command) is set by r2, r3, and r4. maximum frequency occurs when the optocoupler is fully saturated, such as when the llc output moves above the set point during an output load dump. it should be noted that if the maximum fbl pin current is greater than the fmax pin current, the llc gate drivers turn both mosfets off. the start-up current (and therefore the starting frequency), is determined by the value of r3. note that during start-up, c start is a virtual short-circuit, the optocoupler is turned off and all fbl pin current comes from r3. the procedure for selecting the resistor values is as follows. choose r1 this is the main load resistance in series with the optocoupler. a value of 1.8 k w will yield good frequency response with an acceptable maximum collector load current of approximately 2 ma. note that the overall loop gain will be proportional to this resistor value. choose f start (the initial frequency at start-up) f start is typically chosen to be equal to or just less than f max . determine the resistance value that corresponds to the desired f start from figure 16. set r3 to this value. r3 will typically have a value close to that of the fmax resistor. the next step is to set f min . f min is the frequency that the llc needs in order to regulate at full load, f min is determined by the sum of (r3 + r4). look up the resistance value r for the desired f min in figure 16. set r4 according to the equation below. r r r = - 4 3 calculate the value of r2 i fbl(max) is the current that fows into the fbl pin when the optocoupler is saturated. this represents the maximum frequency that the feedback loop can command via the fbl pin. if this current is greater than the fmax pin current (set by the fmax pin resistor), the llc converter may be forced into hysteretic burst-mode in order to regulate the output voltage at zero or light load. if burst-mode is not desired, i fbl(max) must be set less than the fmax pin current. in this case, ensure that there is suffcient dead-time given by the fmax pin resistor. if f max is less than the frequency needed for regulation at light load, then burst mode operation will be required. the relationship between i fbl (fbl pin current) and frequency is given in figure 17. the relationship between i fbl(max) and the resistor values is given below (1): i r r v v i r v v v i v 2 ( ) ( ( ) fb l m ax re f f bl fb l m ax ref cesat fb l f bl ma x d = + - + - - - 3 4 ^ ^ h h (1) v r2 (the voltage across r2) can be defned as: v v v v i v ( ) r r ef cesat fb l f bl ma x d = - - - 2 ^ h (2) we can and then substitute this into (1) and rearrange: (3) where v fbl is a function of i fbl v cesat = v ce of optocoupler in saturation (typical 0.3 v) v d = diode forward voltage drop v ref = 3.25 v (nominal) r4 4 20 2 r3 r2 d1 r1 c opto 1 nf u1b c start c fbl 1 nf gnd vref fbl pi-5276-121108 r 2 r v i r i r v v i r r ( ) ( ) ( ) fb l m ax fb l m ax re f f bl fb l m ax = + - + + 4 2 3 3 4 ] g
rev. f 08/09 14 PLC810PG www.powerint.com llc soft start llc soft start is implemented by c start (figure 7). the llc starts at high frequency and ramps down until output regulation is reached. soft start is required as this allows the resonant tank to begin to oscillate. it also prevents large llc primary currents during start-up that may trip the overcurrent threshold on the isl pin. when the PLC810PG starts up, the fbl pin is internally pulled up to vref (3.25 v), and the llc outputs are disabled. this ensures that the soft start capacitor c start discharged. the fbl pin is then released falling to approximately 0.8 v; the PLC810PG begins sensing the current into the fbl pin and the llc gate drive outputs begin switching. at start-up, the optocoupler will have no current fowing (because the llc converter output is low) and the fbl pin current will be equal to i fblstart . as c start charges, the current into the fbl pin decreases, the llc switching frequency decreases and the llc converter output rises. when regulation is reached, the feedback loop closes and the optocoupler regulates the fbl current. during normal operation, c start remains charged and does not have any current fow. the start-up time constant is: llc protection and auto-restart the isl pin senses llc primary current via a sense resistor in series with the bottom side of the transformer primary. an rc low-pass flter is required, with recommended values of 1 k w and 1 nf respectively. the isl pin has 2 thresholds. the higher threshold, v isl(f) , will immediately shut off and protect the llc mosfets in the event of component failure. the lower threshold, v isl(s) , when exceeded for 8 consecutive cycles, also shuts down the llc protecting against output overcurrent. either fault mode will invoke an auto-restart sequence. when either of these fault conditions occur, the fbl pin is pulled-up internally to vref, discharging the soft start capacitor. the controller counts for 4096 clock cycles, then initiates a new start-up (soft start) sequence. typically 4096 cycles is suffcient to completely discharge the soft start capacitor ensuring that the llc will re-start at frequency f start . layout considerations pfc powertrain layout pfc layout bulk cap 10 nf 500 v boost choke pi-5277-111108 a figure 8. power elements in a boost converter stage. figure 8 shows a typical pfc boost converter power stage using a single bulk capacitor (some designs may use 2 because of the ripple current requirement). with a single bulk capacitor, the bulk capacitor should be closer to the pfc mosfet than the llc mosfets. the pfc mosfet, diode, and bulk capacitor should be mounted close to each other, with short leads connecting them. in addition, a 10 nf-47 nf high frequency bypass capacitor is recommended to reduce emi. it should be connected close to the pfc mosfet and diode, in order to minimize loop area (a in the diagram). this loop area sees the highest di/dt, and thus must be minimized. in some cases, an optional damping resistor in series with the 10 nf capacitor can reduce turn on drain current ringing and consequent emi. the recommended value for this resistor is between 0.2 w and 1 w . llc powertrain layout locating the bulk capacitor if 2 parallel bulk capacitors are used to meet the ripple current requirement, place 1 near the pfc mosfet, and the second near the llc mosfets. if only one bulk capacitor is used, it is recommended that a high voltage decoupling capacitor, (10 nf- 100 nf), is connected across the hvdc bus and primary return, connected with short traces to the llc mosfets. (see c40 in schematic in figure 4, and in pcb layout in figure 9) the llc converter mosfets see high di/dt, and this high voltage decoupling capacitor will reduce emi. high voltage pins three pins on the device have high voltage and high dv/dt because they track the llc mosfet half-bridge output. these are hb, vcchb, and gateh (pins 12, 13, and 14). these pins must be isolated from the rest of the pins on the PLC810PG (extra package isolation is also provided by omitting pins 11 and 15). because these pins have high dv/dt, the traces and components connected to them have to be kept away from low voltage pins. stray capacitance from these nodes to low voltage, (high impedance) pins will cause noise-coupling and erratic operation. maintain 160 mil (4 mm) spacing between these pins, and surrounding low voltage nodes. see highlighted spacing in figure 10. low voltage signal pins all pin decoupling capacitors must be mounted close to the ic and with short traces to the pins. all decoupling capacitors should be returned to the gnd pin, with the exception of the decoupling capacitors for vccl, and vcchb. several pins require external rc low-pass flters. there are the isp, isl, fbp, and fbl pins. the capacitors and resistors should be mounted close to the ic. this will prevent capacitive coupling with high dv/dt nodes. the isp pin is the input pin with the smallest signal and the widest bandwidth. it not only senses the average current in the pfc choke, it also senses peak current in order to perform peak-to-peak current limiting (to protect the pfc mosfet). the current limiting function requires wide bandwidth. c r r star t s tart # # x = r r + 4 4 3 3
rev. f 08/09 15 PLC810PG www.powerint.com figure 10. isolation of high dv/dt pins from low voltage pins and traces. figure 9. location of llc high voltage film decoupling capacitor, c40. pi-5283-111008 isolation spacing use an rc low-pass flter with time constant between 100 ns and 200 ns, mounted near the device. the low-pass flter capacitor should be returned to the gnd pin. mount the pfc sense resistor close to the pfc mosfet. run a dedicated trace from the gnd pin to the junction of the pfc mosfet source and the pfc sense resistor. there should be no other connections on the trace from the gnd pin to the pfc/llc power components. run a dedicated trace from the resistor of the rc low-pass flter on the isp pin to the pfc sense resistor. to avoid loop pick up from di/dt noise that may effect signal integrity, this trace must run alongside the trace from the gnd pin to the pfc mosfet source. layout the pfc driver circuitry near the pfc mosfet. run the trace connecting gatep to the pfc driver circuitry adjacent to the isp trace to the sense resistor. it is preferable to have the gnd trace between the gatep and isp signal traces. this will reduce potential noise coupling from the gatep trace to the isp trace. see figure 12. fbl pin circuitry and optocoupler see figure 13. the fbl pin circuitry should be mounted close to the PLC810PG. the feedback optocoupler is typically
rev. f 08/09 16 PLC810PG www.powerint.com figure 11. gate drive and feedback pcb layout recommendations. mounted far away from the ic. the 2 traces from the optocoupler (emitter and collector), should be run side by side to the fbl circuitry. this minimizes loop area and limits stray di/dt (inductive) noise coupling. gatel and gndl see figure 11. the lines from gatel pin, and the gndl pins, which go to the llc low side mosfet gate and source respectively, should run side by side. the gndl pin should be connected to the llc low mosfet source pin via a ferrite bead. the gate resistor (r28) should also be mounted close to the mosfet. hb and gateh refer to figure 11. the hb and gateh lines should run side by side from the llc high side mosfet to the PLC810PG. the gate resistor (r26) should be mounted close to the mosfet. pi-5281-111308 r15 fbl pin parts near hiperplc route opto traces side-by-side all the way to hiperplc hiperplc hb and gateh traces side-by-side gndl and gatel traces side-by-side gate resistors next to llc mosfets recommended pfc gate drive circuit figure 13 shows the recommended pfc mosfet gate drive circuit. this circuit needs to be placed close to the pfc mosfet. the gate turn-off current is limited by r33, while gate turn-on current is limited by the sum of the values of r33 and r4. resistor r4 also prevents high shoot-through currents fowing through both bjts during switching edges. the resistor r4 is placed in series with the collector of q8 instead of the emitter, as this will prevent negative vbe voltage in q8 which can lead to break down of the junction. resistors r3 and r4 have a strong effect on pfc effciency, and emi. the local 1 m f bypass capacitor, c28, needs to be mounted close to the bjts (q8 and q9). resistor r107 is for keeping the mosfet off when the PLC810PG is unpowered.
rev. f 08/09 17 PLC810PG www.powerint.com figure 12. pfc power and signal layout recommendations. pi-5282-111008 pfc gate drive circuit close to mosfet pfc mosfet, diode, sense resistor, hf bypass cap close to each other dedicated gnd trace to sense r dedicated isp trace to sense r isp, gnd, gatep traces side-by-side figure 13. pfc gate drive circuit recommendation. gatep c28 1 f 25 v q9 fmmt591 q8 fmmt491 q7 spa21n50c3 r4 10 ? r33 10 ? r107 4.7 k? 12 v standby pi-5278-111108
rev. f 08/09 18 PLC810PG www.powerint.com absolute maximum ratings junction temperature ..................................... -40 c to +125 c storage temperature ...................................... -65 c to +150 c theta ja ......................................................................... 35 c/w continuous supply voltage (vcc, vccl) ............... -0.3 v to 15 v llc voltage (hb pin) ........................................... -0.3 v to 600 v llc high side foating supply voltage (vcchb pin with respect to hb pin) ...................... -0.3 v to v ccl llc high side foating output voltage (gateh) ...................... ............................. v hb -0.3 to v vcchb +0.3 llc low side output voltage (gatel) ........... -0.3 v to vccl+0.3 gndp to gnd ............. ........................................ -0.3 v to +0.3 gnd to gndl ............ ........................................ -0.3 v to +0.3 power dissipation .......................................................... 700 mw terminal voltage with respect to gnd 3.3 v tolerant pins ....................................... -0.3 v to v ref +0.3 v isl and isp pins ........................................ -0.65 v to v ref +0.3 v isl and isp pins, max current ....................................... -100 ma i fmax ............................. .................................................. 120 m a dc operating characteristics table 2 lists the minimum, typical, and maximum dc operating voltages and currents for all inputs and outputs of PLC810PG. negative currents fow out of the ic, positive currents fow into the ic. the dc operating characteristics are for a junction temperature of -10 c to 125 c and vcc = 12 v, unless otherwise noted. all voltages are relative to gndp, gndl or gnd (0 v). the pin names that are designated by vcc refer to vcc, vccl and vcchb. the voltages on this pins are respectively to gndp/gnd, gndl and hb. parameter symbol pin notes min typ max units power supply current startup current i ccoff vcc vcc/vccl = uvlo - vcchb = 0 60 120 m a vccl 1.1 2 ma inhibit current i ccinhibit vcc v(fbp) < inh (inhibit state) vcc/vccl = 12 v vcchb = 0 0.7 1.5 ma vccl 1.1 2 operating current i ccon vcc pfc and llc operating 100 khz / 50% duty cycle, gate outputs unloaded, no load on v ref vcc/vccl/vcchb = 12 v 3.0 4.5 ma (vccl + vcchb) 7 9 leakage current i oz isp, isl, fbp, vcomp, fmax 0 < v in < v ref . device in uvlo state. -10 10 m a leakage current i oz isp v in = -0.48 v -10 -800 m a absolute maximum ratings table 1 lists the absolute maximum ratings. stress beyond these limits is likely to cause permanent damage to the PLC810PG. exposure to conditions above recommended operating limits may effect performance and reliability. normal esd handling precautions are recommended. table 1. absolute maximum ratings.
rev. f 08/09 19 PLC810PG www.powerint.com parameter symbol pin notes min typ max units undervoltage lockout vcc start threshold voltage v uvlo(+) vcc device exits uvlo state when vcc exceeds v uvlo(+) 8.2 9.1 10 v vcchb - hb 9.2 vcc shutdown threshold voltage v uvlo(-) vcc device enters uvlo state when vcc falls below v uvlo(-) 7.2 8.1 9.0 v vcchb - hb 8.7 vcc start-up/ shutdown hysteresis v uvlo(hyst) vcc 0.7 1.0 1.3 v llc vco vco frequency range f range fbl llc/pfc synchronized 50 300 khz accuracy of vco min frequency limit f minacc fbl r(fbl) = 100 k w to vref -15 +15 % accuracy of vco max frequency limit f maxacc fmax r(fmax) = 17.8 k w to vref -15 +15 % llc duty cycle dvco gateh, gatel on-time matching gateh (gateh + gatel) 49 50 51 % dead time accuracy t dvcoacc gateh, gatel r(fmax) = 17.8 k w to vref -8 +12 % maximum fmax current i fmax fmax power dissipation limit, i fbl is limited by the current into fmax 135 m a fbl current upper limit i fbl fbl operating range of fbl controlled vco 95 % i fmax fbl equivalent input circuit v in(fbl) fbl fbl input behaves as r in(fbl) in series with v in(fbl) . i (fbl) from 50 to 130 m a 0.65 v r in(fbl) 3.3 k w fbl pin voltage v fbl fbl f vco = 100 khz 0.83 v fbl soft start pull-up resistance r pu(ss) fbl internal pull-up to v ref during soft start reset (4096 f max cycles instantaneous) 900 1500 w fast llc overcurrent fault voltage threshold v isl(f) isl 1.33 1.4 1.47 v slow llc overcurrent fault voltage threshold v isl(s) isl 8 cycle de-bounce 0.385 0.5 0.525 v llc overcurrent fault pulse width t ovl isl minimum time visl exceeds v isl(f) /v isl(s) per cycle to trigger fault 75 ns
rev. f 08/09 20 PLC810PG www.powerint.com parameter symbol pin notes min typ max units pfc pfc overcurrent limit threshold v oc isp static measurement -440 -480 -520 mv pfc output continuous duty cycle range dc pfc gatep 0 100 % pfc error amplifer reference v fbpref fbp 2.2 v pfc error amplifer reference accuracy fbpref fbp -2 2 % pfc overvoltage threshold v ov(h) fbp see note 1 103 105 107 %v fbpref pfc inhibit upper threshold inh fbp see note 1 25 26 27 %v fbpref pfc inhibit lower threshold inl fbp see note 1 22 23 24 %v fbpref transconductance g m fbp v fbp = v fbpref 85 mv 55 85 115 m a/v llc llc shutdown upper threshold v sd(h) fbp see note 1 94.5 95.5 96.5 %v fbpref llc shutdown lower threshold v sd(l) fbp see note 1 63 64 65 %v fbpref reference reference voltage v ref vref loaded with i ref 3.09 3.25 3.41 v current source capability of v ref pin i ref vref 5 ma v ref capacitance c ref vref required external decoupling capacitance on vref pin 1 m f pfc gate output pfc gate output voltage v gate(p) gatep gnd vcc output short-circuit current driving high i sc(h) gatep 25 ma output short-circuit current driving low i sc(l) gatep 60 ma output high voltage v o(h) gatep vcc = 12 v i oh = 1.25 ma 11.5 11.8 v output low voltage v o(l) gatep vcc = 12 v i ol = 5 ma 0.5 0.75 v
rev. f 08/09 21 PLC810PG www.powerint.com parameter symbol pin notes min typ max units llc gate driver llc high side output voltage v gate(h) gateh vhb vcchb llc low side output voltage v gate(l) gatel vcom vccl output high voltage v o(h) gateh, gatel vccl/vcchb = 12 v i oh = -65 ma 11 11.4 v output low voltage v o(l) gateh, gatel vccl/vcchb = 12 v i ol = 130 ma 0.5 1 v output short-circuit current driving high i sc(h) gateh/ gatel vccl/vcchb = 12 v pw <10 m s -0.8 -0.5 a output short-circuit current driving low i sc(l) gateh/ gatel vccl/vcchb = 12 v pw <10 m s 0.9 1.4 a maximum allowed slew rate on hb pin dv hb/dt hb 10 v/nsec turn on rise time (10% - 90%) t r gateh, gatel vccl/vcchb = 12 v 1000 pf load capacitance 50 nsec turn off fall time (90% - 10%) t f gateh, gatel vccl/vcchb = 12 v 1000 pf load capacitance 25 nsec table 2. dc operating characterisitics. notes: 1. this parameter tracks v fbpref .
rev. f 08/09 22 PLC810PG www.powerint.com figure 14. fmax pin pull-up resistor to vref pin vs. dead-time requirement. figure 15. maximum frequency limit vs. pull-up resistor from fmax pin to vref pin. figure 16. pull-up resistance from fbl pin to vref pin vs. switching frequency 50 45 40 35 30 25 20 15 200 250 300 350 400 450 500 550 dead-time (ns) pi-5036-081309 r fmax (k) 300 280 260 240 220 180 200 140 120 160 100 10 20 30 40 50 r fmax (k?) pi-5037-121508 frequency (khz) 130 90 110 70 50 30 50 100 150 200 250 300 frequency (khz) pi-5038-121508 i fbl (a) typical performance characteristics figure 17. fbl pin current vs. switching frequency. 100 10 20 50 10 20 50 100 frequency (khz) pi-5284-121508 r (k ? )
rev. f 08/09 23 PLC810PG www.powerint.com package information and part marking the PLC810PG is packaged in a 24 lead 0.300 pdip package (figure 18 shows the PLC810PG part marking). figure 19 shows the package outline and dimensions. figure 18. PLC810PG part marking. 0911 PLC810PG m59690bb pi-5163-081309 hiperplc marking 1 24 13 12 a b a. power integrations registered trademark b. encapsulation date code (last two digits of year followed by 2-digit work week) c. product identification (part #/package type) d. lot identification code c d
rev. f 08/09 24 PLC810PG www.powerint.com pi-5181-110708 1 0.015 (0.38) min 24 13 pdip-24 (0.300) notes: 1. package dimensions conform to jedec specification ms-001. 2. controlling dimensions are inches. dimensions in millimeters are in parenthesis. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed 0.006 (0.15) on any side. 4. a and b are reference datums on the molded body. c is the datum at the seating plane. 5. dimensioning and tolerancing per asme y14.5m-1994 12 0.240 (6.10) 0.270 (6.86) 1.240 (31.50) 1.260 (32.00) 0.120 (3.05) 0.140 (3.56) 0.115 (2.92) 0.150 (3.81) 0.310 (7.87) 0.400 (10.16) 0.055 (1.40) 0.065 (1.65) 0.009 (0.23) 0.012 (0.30) c 0.015 (0.38) 0.020 (0.51) 0.010 (0.25) m c a b 0.100 (2.54) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) b a figure 19. pdip-24 package marking.
rev. f 08/09 25 PLC810PG www.powerint.com revision notes date a initial release 11/08 b revised fgures and text 11/08 c text, schematic updates 12/08 d schematic updates 02/09 e fixed schematic figure 4 error and removed note 2 from parameter table 05/09 f updated figures 4, 6, 14 and 18 08/09
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